chip-mainline v1.0 Mainline Linux 7.1.5 and Debian 13 on the NextThing C.H.I.P., booting standalone from the onboard NAND with working SSH, WiFi and Bluetooth. Three bugs stood in the way: 1. A mainline clocksource bug that silently kills the scheduler tick. timer-sun4i.c programs the timer interval with evt - TIMER_SYNC_TICKS and returns 0. On the clockevent core's forced minimum-delta path evt IS TIMER_SYNC_TICKS, so it writes zero, which never fires - and by reporting success it stops the core ever retrying. Interrupts keep being serviced, so the board still answers pings while no task is ever scheduled again, and every detector that would catch it is itself tick-driven. timer-sun5i.c has the identical defect. Not board-specific: this affects sun4i/sun5i generally, and these are the two patches proposed upstream. 2. NAND ECC strength. The flash was written at 56-bit; mainline's table says 40, which is the chip's datasheet minimum and correct as a requirement but not as a description of the medium. Fixed in the devicetree. 3. The SPL requires a mkimage-wrapped u-boot-dtb.img. Flashing the raw .bin puts a byte-perfect U-Boot in NAND that the SPL silently rejects. Verified on hardware: NAND rootfs (UBI/UBIFS), USB gadget ethernet and serial console, SSH, WiFi and Bluetooth (RTL8723BS, including pairing and SDP against a real speaker), DRM/lima, cedrus, MMC, NTP. Composite video is verified electrically but has not been confirmed on a display - see the README. Licensed GPL-2.0, as the vendor kernel it was compared against.